FIFO (First-In First-Out) memories are commonly used in data processing and data communication applications. Some FIFO memories have error detection circuitry that is used to determine overrun and underrun condition. One conventional system for detecting these error conditions uses a gray code sequence for the read pointer and the write pointer. A gray code with a minimum Hamming distance is selected for this application. One problem with the gray code solution is that it takes a large number of bits to detect a small number of states. For instance, it takes six bits to define just thirty-two states or locations. It also requires a large number of gates to implement this solution.
Another solution has been to provide an extra status bit with each FIFO location. Whenever a write is performed at a given location, the status bit of that location and its neighbors are written with a “1” value while all others are a “0” value, or vice versa. When the read pointer read data from a location, the corresponding status bit it checked. If the status bit is read as a 0, the read data is considered valid. It the status bit is read as a 1, an error is declared. This technique requires extra circuit area to implement the status bit and writing to the status bits.
Thus there exists a need for FIFO memory error detection circuit and method that reduces the amount of logic gates required to implement the circuit.